Memory is one type of integrated circuitry, and is used in systems for storing data. Memory is usually fabricated in one or more arrays of individual memory cells. The memory cells are configured to retain or store information in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.
Dynamic random access memory (DRAM) is one type of memory, and is utilized in numerous electronic systems. A DRAM cell may comprise a transistor in combination with a charge storage device (for instance, a capacitor). DRAM has an advantage of having rapid read/write; but may be highly volatile (often requiring refresh of several hundreds of times per second). The volatility of DRAM cells may be expressed as the retention time of the DRAM cells. Cells having longer retention times may operate with lower refresh rates as compared to cells with shorter retention times. Lower refresh rates may advantageously reduce power consumption. Modern electronic devices may operate under battery power, and reduced power consumption may lead to improved battery life.
Integrated circuit fabrication continues to strive to produce smaller and denser integrated circuits. Difficulties are encountered as devices are scaled to increasingly smaller dimensions. For instance, even minor structural variations across an array of small-dimension devices may lead to vast differences in performance characteristics of the devices across the array. One of the important performance characteristics of DRAM cells is the retention time. The memory cells across a DRAM array may have different retention times relative to one another. Memory cells having retention times shorter than a preset threshold may be disconnected from the memory array through antifuses or other mechanisms so that they do not influence the overall performance of the memory array. However, even after such memory cells are disconnected, there may still be a substantial variation of retention times across the remaining memory cells within the DRAM array. The refresh rate for the array will be determined by the remaining memory cells having the shortest retention times (i.e., by the worst-performing memory cells remaining in the array). It would be desirable to improve the retention times of the worst-performing memory cells remaining in the array in order to improve (i.e., reduce) the overall refresh rate for the memory array.
Another problem that may occur is that it may be difficult to accurately identify the poor-performing memory cells of a memory array with present testing. Specifically, some memory cells may appear normal under testing conditions, but will then be found to perform to below-normal tolerances under actual use. This may be due defects (for instance, dangling bonds) being cloaked under the conditions of the testing environment (e.g., a dangling bond may be cloaked by having a charge carrier in close proximity to conceal the electrical properties of the dangling bond), and then becoming de-cloaked and problematic under the conditions of actual use (e.g., a charge carrier may migrate away from a dangling bond to reveal the problematic electrical properties of the dangling bond). It would be desirable to develop improved memory cells having electrical properties (e.g., retention times) that consistently carry over from testing regimes to actual use regimes.